HOW TO BOOT CORES of P2041 IN BAREBOARD PROJECTS

[pabloramos]

Hello everybody,

I’m working with P2041RDB for performing a multicore bareboard-project and I want to download all the programs to NOR flash memory and boot them.

I have used the Codewarrior wizard to create an AMP project per core.  For the moment I only use core 0 and 1 and I want that core 0 kicks the core 1 program but it does not work.

• In project core  0, I have add some code in order  to do the boot space translation according to explanation of P2040 Reference Manual. Section 4.3.3. Boot space translation.
• In project core 1, I have changed the configuration addresses in the file P2041RDB_gcc-eabi_ROM.lcf
• I have downloaded core 0 program in NOR flash memory sectors 0xEFF00000 to 0xEFFFFFFF
• I have downloaded core 1 program in the sectors 0xEF820000 to 0xEF91FFFF, in order to fall within the range for the boot window space, assuming that 0xFF…. will be transformed in 0xEF…. For NOR flash memory as it does for core 0.

When I restart the board, core 0 runs correctly but core 1 does not been released.

At this point. I want to know if I am doing a correct boot space translation?

If someone has any idea of these issue please help me. Thanks in advance.

[marius_grigoras]

Hi,

Please take a look over P4080DS SMP scenario from CodeWarrior for PowerArchitecture - is exactly what do you need. Just make a stationary bare-board scenario selecting and select SMP instead of AMP.

Regards,

Marius

[pabloramos]

Hello Marius,

We have done the SMP P4080DS project and use the information to change the amp wizard project to an smp for the 2041RB board, but it does not work.

It seems that when the translation boot takes place the core 0 makes also the translation  and it can not continue with the execution of the code, so it does not print "Welcome to Codewarrior" message.

As we understand, we add the smp_target.c and smp_target.h files to the project. We add the compiler variable -DSMPTARGET. And we change some files variables : MAX_NUM_OF_CORES

from 8 to 4, CORES_MASK to 0x0000000F and edit the definition of INIT_MMU_DDR in smptarget.c because the DDR TLB entry in the board 2041RB is the number 7 while in P4080DS is number 8. Finally we have added the stack addresses for the 4 cores and the spin section in the .lcf file.

In order to test if changes in code are correct, we have removed the part of traslation boot in the start_e500mc_crt0.cpp and everything works. So, we decide to call the translation boot routine after the core 0 changes the spin_table(initSmp) function, but it is the same, the other cores do not do anything and the core 0 does not continue with the code.

Could you explain us how the translation boot process works (step by step please) because in the reference manual the explanation is too general and we could not understand it?

Thanks in advance.

Best regards,

Pablo

[pabloramos]

Hello Marius,

Thank you for your fast answer.  We have  a problem becuase our CodeWarrior  (10.3) license does  not allow to create SMP projects. This option is disabled in the prosessing model window while creating the bareboard project. Do you have any document where we can find this information?

Best regards,

Pablo

[pabloramos]

Hello Marius,

Finally we have done the 4080DS SMP scenario project. We are going to do what you suggest and if we have some questions we write to you.

Thanks a lot.

Pablo