MPC5643L FCCU interrupts not occuring

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MPC5643L FCCU interrupts not occuring

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twp
Contributor III

We are developing a system in which we need to log alarms and faults generated by the FCCU on the MPC5643L.  To test this I am Injecting fake critical and non-critical faults, critical faults should generate an NMI which we have attached a logging function to, and the interrupt controller has a handler assigned to 250 which should catch the alarm interrupts. This code has previously worked and I managed to record alarm codes to shadow flash, however neither of these handlers are now being called.  I know that the critical fault injection is still functioning as it generates a RESET and transition to SAFE mode but there is no response to the non-critical fault injection.

 

Is there any way in which the interrupts could be disabled?  The register FCCU.IRQ_EN only has a single field for the Configuration Time Out interrupt.

 

The non-critical fault I am testing is enabled and has a timeout enabled so the FCCU should transition to the ALARM state.

 

Any help appreciated,

 

Tom.

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petervlna
NXP TechSupport
NXP TechSupport

Hi Tom,

If you take a look at table Table 285. FCCU mapping of non-critical faults in reference manual you will see:

pastedImage_3.png

Under Set/clear injection (inject fault) - the faults which can be injected. For ADC self-test (NCF10 & NCF11) it is [Yes - by ADC itself)]

This means NCF 10 and 11 can be injected onyl by ADC peripheral.

If you take a look on ADC self-test registers: Table 43. STCR2 field descriptions


pastedImage_13.png

So, for injection of this particular fault you need to set ADC.STCR2[SERR] = 1. Then you will see it in FCCU.NCF_S register.

If you need any further help do not hesitate to ask.

Ciao,

Peter

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vijayravi
Contributor II

How to clear this ADC critical fault after injecting. Even if I clear I_SAFE bit, it remains in fault state.

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petervlna
NXP TechSupport
NXP TechSupport

[Peter] - In FCCU NCF Enable Register you can mask the reaction following a fake non-critical fault.

FCCU NCFS Configuration Register (FCCU_NCFS_CFG0..7) the reaction on fault. As you didn’t share your FCCU configuration, please make sure you have your FCCU configured properly.

Is there any way in which the interrupts could be disabled?

[Peter] – Yes, even whole reaction can be disabled via FCCU configuration registers.

The external interrupt is asserted if any interrupt status bit of the FCCU_IRQ_STAT is set and the respective enable bit of the FCCU_IRQ_EN register is also set.

The register FCCU.IRQ_EN only has a single field for the Configuration Time Out interrupt. The non-critical fault I am testing is enabled and has a timeout enabled so the FCCU should transition to the ALARM state.

[Peter] – Yes, it should on timeout trigger and interrupt

[Peter] - To avoid any speculations, I would like to see your FCCU configuration.

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twp
Contributor III

Hi Peter,

Thank you for the reply.  the FCCU configuration is below.  At this point it is fairly standard as the first stage in our development is to get the interrupts up and running.

FCCUCTRL0x000001c00xffe6c000`Physical
FCCUCTRLKnon-readable0xffe6c004`Physical
FCCUCFG0x003f0e3f0xffe6c008`Physical
FCCUCFCFG00xffffffff0xffe6c00c`Physical
FCCUCFCFG10x0000ffff0xffe6c010`Physical
FCCUCFCFG20x000000000xffe6c014`Physical
FCCUCFCFG30x000000000xffe6c018`Physical
FCCUNCFCFG00xffffffff0xffe6c01c`Physical
FCCUNCFCFG10x000000000xffe6c020`Physical
FCCUNCFCFG20x000000000xffe6c024`Physical
FCCUNCFCFG30x000000000xffe6c028`Physical
FCCUCFSCFG00xaaaaaaaa0xffe6c02c`Physical
FCCUCFSCFG10xaa82800a0xffe6c030`Physical
FCCUCFSCFG20xaa8008000xffe6c034`Physical
FCCUCFSCFG30x000000000xffe6c038`Physical
FCCUCFSCFG40x000000000xffe6c03c`Physical
FCCUCFSCFG50x000000000xffe6c040`Physical
FCCUCFSCFG60x000000000xffe6c044`Physical
FCCUCFSCFG70x000000000xffe6c048`Physical
FCCUNCFSCFG00x0000aaaa0xffe6c04c`Physical
FCCUNCFSCFG10x000000000xffe6c050`Physical
FCCUNCFSCFG20x000000000xffe6c054`Physical
FCCUNCFSCFG30x000000000xffe6c058`Physical
FCCUNCFSCFG40x000000000xffe6c05c`Physical
FCCUNCFSCFG50x000000000xffe6c060`Physical
FCCUNCFSCFG60x000000000xffe6c064`Physical
FCCUNCFSCFG70x000000000xffe6c068`Physical
FCCUCFS00x000000000xffe6c06c`Physical
FCCUCFS10x000000000xffe6c070`Physical
FCCUCFS20x000000000xffe6c074`Physical
FCCUCFS30x000000000xffe6c078`Physical
FCCUCFKnon-readable0xffe6c07c`Physical
FCCUNCFS00x000000000xffe6c080`Physical
FCCUNCFS10x000000000xffe6c084`Physical
FCCUNCFS20x000000000xffe6c088`Physical
FCCUNCFS30x000000000xffe6c08c`Physical
FCCUNCFKnon-readable0xffe6c090`Physical
FCCUNCFE00x01d3fcff0xffe6c094`Physical
FCCUNCFE10x000000000xffe6c098`Physical
FCCUNCFE20x000000000xffe6c09c`Physical
FCCUNCFE30x000000000xffe6c0a0`Physical
FCCUNCFTOE00x01fbffff0xffe6c0a4`Physical
FCCUNCFTOE10x000000000xffe6c0a8`Physical
FCCUNCFTOE20x000000000xffe6c0ac`Physical
FCCUNCFTOE30x000000000xffe6c0b0`Physical
FCCUNCFTO0x0000ffff0xffe6c0b4`Physical
FCCUCFGTO0x000000060xffe6c0b8`Physical
FCCUSTAT0x000000000xffe6c0c0`Physical
FCCUCFF0x000000000xffe6c0d8`Physical
FCCUNCFF0x000000000xffe6c0dc`Physical
FCCUIRQSTAT0x000000000xffe6c0e0`Physical
FCCUIRQEN0x000000000xffe6c0e4`Physical
FCCUXTMR0x000000000xffe6c0e8`Physical
FCCUMCS0x000080830xffe6c0ec`Physical

Regards,

Tom.

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petervlna
NXP TechSupport
NXP TechSupport

Hi Tom,

Your FCCU configuration seems fine to me. Except one thing, you need to enable interrupt on Timeout.

The external interrupt is asserted if any interrupt status bit of the FCCU_IRQ_STAT is set and the respective enable bit of the FCCU_IRQ_EN register is also set.

pastedImage_0.png


Also do not forget to enable interrupts in INTC

pastedImage_1.png

And to enable external interrupts in MSR[EE]=1


Peter

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twp
Contributor III

Hi Peter,

Another question on this subject.  When an ALARM interrupt occurs it is possible to search through the FCCU.NCF_S[] registers to find the source of the fault. If an NMI occurs and it was triggered by a critical fault it can be seen in the FCCU.CF_S[] registers, but if it was due to a timeout of a non-critical fault there doesn't seem to be a register which will give the source.  I was expecting a set of 'Non-critical fault timeout occurred' registers.  In 99% of occurrences there won't have been a second ALARM generated so searching FCCU.NCF_S[] will give you the source, but it isn't guaranteed to be the correct source of the FAULT state.  Am I missing a trick here?

Tom

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petervlna
NXP TechSupport
NXP TechSupport

[Peter] – If it was due to a timeout of non-critical fault, then the source of fault is still the same and it is stored in NCF status register. There is a possibility to trigger interrupt on timeout where you can analyze why was not possible to recover from fault state. But the original cause of the fault is still in NCF status register. As long as the fault remains in status register the FCCU will trigger appropriate actions.

I see no reason from safety point of view to store time-out event in some special register if the original fault persist and micro can’t operate normally. If the fault is removed micro won’t get into the alarm state. So why to analyze the timeout?

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twp
Contributor III

Hi Peter,

I agree, it has no bearing on the safety of the system.  I was considering it from a diagnostics point of view.  This isn't really an issue, I was just checking that I'm not missing a trick for determining the cause.

Reading back the NCF status register after injecting the fault I can see that it is not set.  However if I change that single line of code to inject a critical fault I get an immediate reset and transition to safe mode.

Kind regards,

Tom.

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petervlna
NXP TechSupport
NXP TechSupport

After injecting of NCF, are you reading NCF_S registger correctly like described below?

The SW application executes the FCCU_NCFSx read operation by the following sequence:

• to set the OP10 operation into the FCCU_CTRL.OPR field

• to wait for the completion of the operation (FCCU_CTRL.OPS field)

• to read the FCCU_NCFSx register

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twp
Contributor III

Hi Peter,

Yes, I am following that procedure.  It correctly reads the fault status register values if I generate an ADC self-test failure.  The whole interrupt and logging code works if it is a system generated fault but not if I inject a fault.

Tom.

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petervlna
NXP TechSupport
NXP TechSupport

Hi Tom,

If you take a look at table Table 285. FCCU mapping of non-critical faults in reference manual you will see:

pastedImage_3.png

Under Set/clear injection (inject fault) - the faults which can be injected. For ADC self-test (NCF10 & NCF11) it is [Yes - by ADC itself)]

This means NCF 10 and 11 can be injected onyl by ADC peripheral.

If you take a look on ADC self-test registers: Table 43. STCR2 field descriptions


pastedImage_13.png

So, for injection of this particular fault you need to set ADC.STCR2[SERR] = 1. Then you will see it in FCCU.NCF_S register.

If you need any further help do not hesitate to ask.

Ciao,

Peter

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twp
Contributor III

Thanks Peter,  I had missed the meaning of that column in the table.

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twp
Contributor III

Hi Peter,

I've configured my device to fail the ADC self-test routine, thus generating an non-critical fault.   I can see that it is generating an ALARM state then progressing to the FAULT state and both the INTC and NMI interrupts are being generated and being caught in our application.  However, if I switch to the fault injection method I don't get any interrupts.  It appears either I am missing something on the fault injection side or injected faults don't generate interrupts.  Does the FCCU need to in a particular state or be sent an OP code before a fault can be injected?

Tom.

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petervlna
NXP TechSupport
NXP TechSupport

"Does the FCCU need to in a particular state or be sent an OP code before a fault can be injected?"


FCCU can inject faults in Normal state.

First please make sure that your FCCU sw routine is injecting NCF correctly. Inject the fault and read  FCCU NCF Status Register to verify that fault was recorded in  FCCU NCF Status Register.

You need to set OP10 [01010 Read the NCF status register (refer to the FCCU_NCFS register) [OP10].] to properly read the status.

pastedImage_0.png


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