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32-beat burst transfer with SDMA in i.MX6Q.

Question asked by Keita Nagashima on Apr 1, 2014
Latest reply on Apr 23, 2014 by Lei Ge
Branched to a new discussion

Dear Sir or Madam,

 

Hi.

I'd like to realize below transfer om i.MX6Q.

4Byte(32bit) : 32-beat burst transfer (=128Byte)

 

[Observed Result]

Burst Access by using SDMA.

Write:

DRAM to EIM(0x08000000) --> (7 beat + 1 beat) x 4

DRAM to EIM(0x0C000000) --> (7 beat + 1 beat) x 4

Read:

DRAM to EIM(0x08000000) --> (8 beat) x 4

DRAM to EIM(0x0C000000) --> (8 beat) x 4

 

[Question]

Refer to 55.4.3.1 Burst DMA Unit in MCIMX6DQRM(Rev.1).

----

Perform up to 8-beat read and write bursts to the ARM platform memory, which

optimizes throughput when accessing SDRAM-type devices because of an internal,

36-byte FIFO

----

 

=Q1=

When using SDMA, is the 8-beat burst transfer the maximum?

Is there a way of realizing 32-beat burst transfer?

 

=Q2=

In case of "Write" operation, it became (7 beat + 1 beat) x 4.

What setting is necessary for the 8-beat burst transfer?

 

Keita

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