Dear Sir or Madam,
I'd like to realize below transfer om i.MX6Q.
4Byte(32bit) : 32-beat burst transfer (=128Byte)
Burst Access by using SDMA.
DRAM to EIM(0x08000000) --> (7 beat + 1 beat) x 4
DRAM to EIM(0x0C000000) --> (7 beat + 1 beat) x 4
DRAM to EIM(0x08000000) --> (8 beat) x 4
DRAM to EIM(0x0C000000) --> (8 beat) x 4
Refer to 126.96.36.199 Burst DMA Unit in MCIMX6DQRM(Rev.1).
Perform up to 8-beat read and write bursts to the ARM platform memory, which
optimizes throughput when accessing SDRAM-type devices because of an internal,
When using SDMA, is the 8-beat burst transfer the maximum?
Is there a way of realizing 32-beat burst transfer?
In case of "Write" operation, it became (7 beat + 1 beat) x 4.
What setting is necessary for the 8-beat burst transfer?