I would like to configure a Xilinx FPGA, using SelectMAP configuration mode, over the EIM bus on a i.MX6 D/Q. Are there any application notes or any information on how to set up the EIM bus to accomplish this?
We've managed to achieve a byte-wide boot of a Spartan 6 device using the EIM, it wasn't too hard.
The main thing to get right is the byte and bit order. The iMX6 deals in 32bit memory locations, so EIM writes are always 32 bit. If your bus is byte-wide then this means you have to pack each write with 4 bytes of your FPGA design. We also found we had to reverse the bit order.
A couple of tips:
Hope that helps.
Are you using synchronous EIM mode and BCLK to clock in the configuration data?
Or, asynchronous mode with a free-running clock connected to CCLK?
If you are using synchronous mode, won’t the BCLK for the address phase(ADV low) clock in incorrect data?
We're using asynchronous mode with EIM_BCLK output connected to the FPGA.
From you postings, I gather that you were using asynchronous mode with BCLK tied to CCLK and BCLK was continuously running.
The confusing part is your comment about chip select. It is my understanding that you used a GPIO to control the CSI_B input of the FPGA during configuration and kept it low during the loading of the configuration data.
If that is correct, won’t the free-running CCLK clock in any data that is on the EIM data bus while CSI is low? For example, the CCLK will be running, and CSI will be low, during the address phase of the asynchronous access where the data may be invalid.
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