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PF0100A OTP

Question asked by Satoshi Shimoda on Mar 25, 2014
Latest reply on Mar 26, 2014 by Joshevelle

Hi community,

 

I have a question about PF0100A OTP.

Please see Table 2 in MMPF0100 datasheet (Rev.7.0).

It says "It is required to set FUSE_POR1, FUSE_POR2, and FUSE_POR3 bits during OTP programming." in description of OTP_FUSE_PORx register setting during OTP programming.

I understand user should note this difference only when using MMPF0100NPAxx.

On the other hand, all MMPF0100FxAxx OTP is programmed before shipping, so FUSE_PORx bits have already been set to "1" for MMPF0100FxAxx when user get the chip.

So user can ignore this difference when using MMPF0100FxAxx.

Is my understanding correct?

 

 

Best Regards,

Satoshi Shimoda

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