First of all, I am a beginner. Recently encountered a problem when using Flexbus, connect FPGA. FB_ALE output signal wrong(See Appendix,Described in the reference manual, which should be active high).
Register set(In BSP Configuration) ：PAR_FBCTL = f5.(set FB_ALE),PPMLR0 = fbc2f300.(enable FB Clock).
I would like to ask whether my configuration is incorrect, please enlighten me.
Code in Annex
Original Attachment has been moved to: Flexbus.txt.zip