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Single Synchronous EIM Access

Question asked by Tom Dickson on Mar 25, 2014
Latest reply on Apr 2, 2014 by Tom Dickson

Hi,

 

     Figures 12 and 13 of the i.MX6 Dual/Quad Applications Products for Industrial Products data sheet show single read and write synchronous accesses on the EIM bus.  Can someone explain how those are achieved?

 

     I assume an AXI read or write with burst length of 1 and burst size of 2(for a 16 bit data bus) would cause a single read or write synchronous access?  I am accessing registers in an FPGA and do not want to burst any data to/from the registers - only read or write single data words.

 

     Would accessing a non-cached uint16 cause the proper AXI access?

 

     And, is BL ignored if a single AXI access is used?

 

Thanks for your time,

Tom

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