PowerPC P2041(E500MC), How to access L1 DCache in u-boot stage?

[jiaguo]

In u-boot for P2041RDB, the L1 DCache is used as init ram, and the stack is allocated from init ram for jumping into C environment.

u-boot setup TLB1 entry14 for L1 DCache:

create_tlb1_entry 14, \ 
 1, BOOKE_PAGESZ_16K, \ 
 CONFIG_SYS_INIT_RAM_ADDR, 0, \ 
 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ 
 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 

u-boot allocate init ram in data cache:

/* Allocate Initial RAM in data cache. */
lis r3,CONFIG_SYS_INIT_RAM_ADDR@h 
ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 
mfspr r2, L1CFG0 
andi. r2, r2, 0x1ff 
/* cache size * 1024 / (2 * L1 line size) */ 
slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) 
mtctr r2 li r0,0 
1: 
dcbz r0,r3 
dcbtls 0,r0,r3 
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE 
bdnz 1b 

I would like to ask how to access the allocated L1 DCache?

As the code depicted, CONFIG_SYS_INIT_RAM_ADDR(0xffd0_0000) is mapped to CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH|CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, and CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH is: 0xf and CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW is: 0xffd0_0000, why should I use that physical address?

If someone familiar with this issue, please help me. Thanks in advance.

Best Regards,
Jia

[scottwood · Accepted solution]

You access it with load and store instructions, and a TLB entry that maps that physical address.  The physical address is arbitrary and just needs to not conflict with anything else.