I am trying to decipher the KL26 reference manual KL26P121M48SF4RM_rev3.2 on how to use a bus clock pre-divided by 2. The figure 28-1 on pg 479 and the section 28.4.1 description text indicates that the bus clock can be pre-divided by 2 by selecting the appropriate CFG1[ADICLK] setting. The reference manual CFG1 register description on page 486 shown below does not include this possibility. I have been unable to find anywhere else in the reference manual where it gives the ADICLK setting for this half bus clock source. Is it known if this clock source option is unavailable on the KL26 and the diagram/text is in error or is the register description in error (i.e. is ALTCLK2 actually the bus clock divided by 2)?
Input Clock Select
Selects the input clock source to generate the internal clock, ADCK. Note that when the ADACK clock
source is selected, it is not required to be active prior to conversion start. When it is selected and it is not
active prior to a conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at the
start of a conversion and deactivated when conversions are terminated. In this case, there is an
associated clock startup delay each time the clock source is re-activated.
00 Bus clock
01 Alternate clock 2 (ALTCLK2)
10 Alternate clock (ALTCLK)
11 Asynchronous clock (ADACK)
Thank you for your assistance,