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i.MX6 IPU DIsplay interface sync pulses

Question asked by Geisreiter Andreas on Mar 20, 2014
Latest reply on May 30, 2014 by Qiang Li - Mpu Se

Hi,

 

we are working at the moment with i.MX6DL. I tried to setup new display support (RGB interface) in Bootloader U-Boot. There is a struct available, where I can define all the display timings:

 

.mode= {
.name           = "wvga-rgb",
.refresh        = 57,
.xres           = 800,
.yres           = 480,
.pixclock       = 33260,
.left_margin    = 42,
.right_margin   = 86,
.upper_margin   = 10,
.lower_margin   = 33,
.hsync_len      = 128,
.vsync_len      = 2,
.sync           = 0,
.vmode          = FB_VMODE_NONINTERLACED

 

But there I miss the activity of the sysnc pulses, e.g. if hsync is active high or active low. I also searched in the user manual about the i.MX6 IPU register where I can set the active high or low information but I can't find it.

So can anybody tell me in which registers I can set the following informations:

V-Sync: Active high or low

H-Sync: Active high or low

Pixel Clock: Data is driven on falling or rising edge

Output enable: Active high or low

Data lines: inverted or not

 

If anybody can tell me how I can do this in U-Boot it would also help.

 

Best regards,

Andreas

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