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Question about mpc85xx(P2040) startup using Nor Flash

Question asked by Hook Guo on Mar 19, 2014
Latest reply on Mar 24, 2014 by alexander.yakovlev

I'm porting u-boot to P2040 based board these days.

As u-boot/arch/powerpc/mpc85xx/start.s commented:

The processor starts at 0xffff_fffc and the code is first executed in the last 4K page in flash/rom.

In u-boot/arch/powerpc/mpc85xx/resetvec.S:

.section .resetvec,"ax"

b _start_e500

And in linker script:




} :text = 0xffff


The E500MCRM Chapter 6.6 mentioned:

This default TLB entry translates the first instruction fetch out of reset(at effective address 0xffff_fffc).

This instruction should be a branch to the beginning of this page.

So, if I configure the HCW to let powerpc boot from Nor Flash, why should I suppose that the Nor Flash's

last 4K is mapped to 0xffff_f000~0xffff_ffff? Since there're no LAW setup yet and the default BR0/OR0 of Local Bus

does not match that range.


Best Regards,

Hook Guo