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i.MX6 - question about DDR memory bandwidth utilization

Question asked by Marcin Formruga on Mar 18, 2014
Latest reply on Mar 27, 2014 by Yuri Muhin

Hi All,

 

Our board has i.MX6DL with 32@400MHz DDR3 modules. The memory has a 800 Mb/s per pin, which gives 3200 MB/s. Of course this is theoretical value only, but based on http://www.xilinx.com/support/documentation/white_papers/wp383_Achieving_High_Performance_DDR3.pdf, page 6, Table 1, bandwidth efficiency (clock_cycles_transferring_data / total_clock_cycles * 100) can vary (for optimized memory controller) between 57 % - 90 %.

 

The problem is that based on values from i.MX MMDC profiling mechanism, we can't get efficiency larger than 50 %.  I found that Francisco Dominguez in thread https://community.freescale.com/message/328259#328259, also wrote about 50 % of efficiency. The question is why?

 

The second question is about changing way of DDR connection from x32 to x64. What is real improvement in bandwidth? I think that double a bandwidth is not possible. Most of AXI masters are 64-bit, so improvement is possible only due to use of upsizers in NIC-301, am I right?

 

Thanks,

Marcin

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