Dear Sir or Madam,
I have a question about burst transfer of SDMA in i.MX6DQ.
Refer to 22.5.8 AXI (Master) Bus Cycles Support in i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 1, 04/2013.
There are below descriptions.
Only 32-bit word size accesses are supported for burst
Only 8-bit (1 byte), 16-bit (2 byte) and 32-bit (4 byte) word
size supported for single access.
Maximum number of burst length is 16.
=About DMA burst transfer=
When the burst accesses with following use case, is it supported except 32 bits word size access, too?
Source : LPDDR2
Destination : EIM
Source : EIM
Destination : LPDDR2