I am using P1022 processor in my design. Boot device is 8 bit NAND flash (4Gbit) attached using FCM mode. The Reset logic is done through FPGA only. Reset logic was done as per details given in "Electrical characteristics"`
From the power on and till the completion of FPGA configuration, the processor was held in Reset state. After completion of FPGA configuration, it releases the Reset signals to Logic High. (In Electrical characteristics- Reset timing details it was given as, Reset signals to be driven as low for minimum 25us from High state. But in our module it was kept low continuously till the completion of FPGA configuration(for about two seconds) and directly releases to High state).
The u-boot was successfully loaded in NAND flash through Codewarrior tool. After power on & Reset releasing to Processor, the processor tries to boot but it get struck at one point and it didn't boot further. We had put one notification print message before copying code from Flash to DDR SDRAM. This message was displayed in putty window in improper manner and doesn't boot further.
We have an option to give a Reset through one On-board switch, if we give Reset through this switch, the processor again boot and struck at the same point.
In the same situation, if we connect a Codewarrior and give a Reset or Resume command from Codewarrior IDE, the processor was booted successfully without any problem. After booting also if I give an Onboard Reset or Soft reset to the processor, the processor Resets and booted normally.
Clarification needed :
1). What is happening inside the processor while giving the Reset through Codewarrior.
2). What is happening inside the processor while giving the Resume through Codewarrior.
3). Any registers are updated / sequences are executed in processor through JTAG interface while asserting the Reset or Resume through Codewarrior`
Please clarify the details at earliest.
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