We are using a Freescale MMA8452Q accelerometer in our design. The layout guidelines (AN4077) have the following recommendations that I would like clarification on:
- Do not place any components or vias at a distance less than 5 mm from the package land area. This may cause additional package stress if it is too close to the package land area.
- Signal traces connected to pads are as symmetric as possible. Put dummy traces on NC pads in order to have same length of exposed trace for all pads.
In the same application guide is a photo of the Freescale demo board which appears to violate these recommendations having vias immediately around the package as well as a decoupling capacitor:
My question is - how essential is the clearance for vias and components to the MMA8452Q? Ideally I would like the decoupling closer than 5mm to the device. Also what is the mechanism for 'causing package stress' if a capacitor is within 5mm of the QFN?
Also, do I really need to put dummy traces on the NC pads?