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Unable to access IPU Registers

Question asked by Aditya Kousik on Feb 28, 2014
Latest reply on Apr 1, 2014 by Karina Valencia Aguilar
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Hello all,

 

I'm trying to get a custom kernel working and for the framebuffer, access to the IPU registers is fundamental. IPU_1_BASE is at 0x02600000. But any sort of read/write access to any of the registers from here throws an error. For example, I tried stopping the DI0 pixel clock (IPUx_DI0_GENERAL) by setting it to 0. But it throws an error.

 

What I have done so far:

     1. I read from here about enabling the clocks through CCM. Which I have done so far. I wrote 0x3  to both ipu_1_clk_enable and ipu1_ipu_di0_clk_enable in CCM::CCGR3.

     2. I've also configured IOMUXC to IPU_enable through IOMUXC::GPR2 's CH0_MODE, BIT_MAPPING_CH0, DATA_WIDTH_CH0 and DI0_VS_POLARITY.

 

A R/W access to IPU module still doesn't work. Clearly, what I've done so far is either wrong/incomplete.

 

What is the procedure to get the IPU (and by extension, the framebuffer) enabled and working? I couldn't find the particular answer in the reference manual. Any idea/assistance would be deeply appreciated.

 

Thanks and regards

Aditya Kousik

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