I have MK10DN512Z VLL10 with a bareboard project that has PE attached to it.
I have my SPI0 as my slave and sending data to it from outside.
1- I am not sure why the interrupt event "SlaveSPI0_OnBlockReceived" happens twice when I send data!
What I did, every time that I receive a 4 block data (each block is 16 bits), I see that the first time interrupt happens, and so I get the 4 block, but the second time that interrupt happens I don't have anything to pick and so it sends zeros only! But I only send 4 blocks from my master. I don't send 8 blocks at all.
Another thing I did in my interrupt event I flush the RX to make sure overflow is not a problem:
void SlaveSPI0_OnBlockReceived(LDD_TUserData *UserDataPtr)
{
printf("==========ISR event: SPI0 receive a block=========\n");
if ((IO_READ32(Rx0SPI0)) != 0)
{
print_RX_FIFO();
inbuff = (IO_READ32(Rx0SPI0)<<16);
inbuff |= IO_READ32(Rx1SPI0);
extended_inbuff = (IO_READ32(Rx2SPI0)<<16);
extended_inbuff |= IO_READ32(Rx3SPI0);
}
RX_FIFO_flush();
TX_FIFO_flush();
DataReceiveFlagSlave1 = TRUE;
}
and this is what I see in my shell:
==========ISR event: SPI0 receive a block========= (THIS IS FIRST TIME)
SR_SPI0 = 0x3344
RX0 = 0x1122 RX1 = 0x3344
RX2 = 0x5566 RX3 = 0x7788
==========ISR event: SPI0 receive a block========= (THIS IS SECOND TIME, HUH!!!)
2- I also looked into SPI0 Interrupt vector at address: 0xA8 and also the normal interrupt at address 0x84. I see that the values inside these vectors do not change, which is surprising to me!!! I expect these values change! Where can I look into what register or vector to see what is triggering the second interrupt?
The processor has only one handler for all SPI0 and one for all SPI1 interrupts.
There are several possible sources of SPI0 interrupt.
- End of Queue reached (EOQF)
- TX FIFO is not full (TFFF)
- Transfer of current frame complete (TCF)
- Attempt to transmit with an empty Transmit FIFO (TFUF)
- RX FIFO is not empty (RFDF)
- Frame received while Receive FIFO is full (RFOF)
They are enabled by the SPI0_RSER register. You probably have two interrupts enabled (for example TCF and RFDF).
You need to check register SPI0_RSER to see which interrupts are enabled and register SPI0_SR to see which conditions have caused the interrupt.
Hope this helps