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CWTAP_GDB_P1010_P4080 (P1010 and P4080 XML and Initialization for GDB debugging)

Question asked by melbournebob on Feb 26, 2014
Latest reply on Jan 23, 2017 by Saqlain Raza

I'm using the P1010RDB along with a CodeWarrior TAP and  Power Architecture TIP.

I'm having a little trouble understanding the settings for the TLB1 entries.

I downloaded the CW_TAP_GDB_P1010_P4080 (filename gdb_test_ccs_365.tar.gz), I found the only documentation explaining the three longwords (96 bits) displayed for a TLB1 table entry are in the comments as follows in the bin/p1010_init.gdb file:

    #                                            0            20   21        29             39        40        41

    # data format of l2mmu_cam = EPN(20)::TS::TID(8)::MASK(10)::IPROT::VALID::IPROT_dup::

    #                                            RPN(24)::UR::UW::UX::SR::SW::SX::X(2)::WIMGE(5)::U(4)::TSIZE(4)::SHEN::IPROT::spare

    #                                            42           66   67   68    69   70   71   72     74             79     83            87       88        89


After the comment above the p1010_init.gdb file sets the TLB1 entrys:

   echo Set TLBs\n

   set $mmu_l2_tlb1_2={0xE0000000, 0x1FC38000, 0x07140A80}

   set $mmu_l2_tlb1_3={0xFE000000, 0x7FC3F800, 0x07140E80}

   set $mmu_l2_tlb1_4={0xFF000000, 0x7FC3FC00, 0x07140E80}

   set $mmu_l2_tlb1_5={0x80000003, 0xFFC20000, 0x07141480}

   set $mmu_l2_tlb1_6={0xEFC00000, 0x0FC3BF00, 0x07140880}

   set $mmu_l2_tlb1_7={0xEFB00000, 0x0FC3BEC0, 0x07140880}


I examined the contents of the TLB before any of the modifications were written above (I placed an "info registers" before the first "set $mmu_l2_tlb1_2 ...") and it shows the following for the zero'th entry in TLB1:

   mmu_l2_tlb1_0 {0xfffff000, 0x1c3ffff, 0xc71402c0}

As I understand it this entry should be mapping the last 4 Kbytes of memory space (flash) that encompasses the reset vector (0xFFFFFFFC).

The TLB1 definition in the comments show the 'spare' field is the least significant 7 bits of the 3rd word.

Why does the default TLB1 entry 0 have a bit set in this 'spare' field?