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SSI_LDD clock bug

Question asked by Marc Lindahl on Feb 24, 2014
Latest reply on Feb 25, 2014 by Vojtech Filip

Setting the "Master Clock" to "Input Pin" in SSI_LDD results in this code in Audio0_Init (default name):

 

  /* I2S0_MCR: MOE=0 */

  I2S0_MCR &= (uint32_t)~(uint32_t)(I2S_MCR_MOE_MASK); /* Disable MCLK divider */

  while ((I2S0_MCR & I2S_MCR_MOE_MASK) != 0U) {} /* Wait for MCLK disable*/

  /* I2S0_MDR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FRACT=0,DIVIDE=0xF9 */

  I2S0_MDR = (I2S_MDR_FRACT(0x00) | I2S_MDR_DIVIDE(0xF9)); /* Configure Mclk divide ratio */

  /* I2S0_MCR: DUF=0,MOE=1,??=0,??=0,??=0,??=0,MICS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

  I2S0_MCR = (I2S_MCR_MOE_MASK | I2S_MCR_MICS(0x00)); /* Configure Mclk source */


Last line: MOE is set, making the MCLK line an output.


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