I have some questions about correspondence between i.MX6Q IBIS model and register setting.
I use "ddr3_sel11_ds111_mio(DDR, 1.5V, ddr3 mode, 34 Ohm driver impedance)" mode for DRAM_SDCLK_1.
Is this case, how should I set DDR_SEL field and DSE field of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P regisnter (chapter 36.4.353) in IMX6DQRM (rev.1)?
According to mode name, I think DDR_SEL= 11b from sel11, and DQE = 111b from (ds111).
Is this correct?
If the anwer for Q1 is correct, how about other setting?
Default values are set?
For example, there is no "odt" in the mode name, ODT = 000b in this case?
I use "ddr3_sel11_ds111_mio（DDR, 1.5V, ddr3 mode, 34 Ohm driver impedance)" for DRAM_SDQS0 write access, and "ddr3odt_t60_sel11_mi（DDR, 1.5V, ddr3 mode, 60 Ohm ODT)" for read access.
I think DQS is bi-drectional signal, also DQ, then can I set DRAM_SDQS0 IOMUX setting (e.g. DDR_SEL, DSE, etc) for write access and for read access individually?
I use "gpiohv_ds111_sr111_mio GPIO, 3.3V,extra drive,fast sr,max fsel" mode for ENET_TXD0.
When use this mode, how should I set each field of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA00 register (chapter 36.4.317)?