Correspondence between i.MX6Q IBIS model and register setting.

[satoshishimoda]

Hi community,

I have some questions about correspondence between i.MX6Q IBIS model and register setting.

[Q1]

I use "ddr3_sel11_ds111_mio(DDR, 1.5V, ddr3 mode, 34 Ohm driver impedance)" mode for DRAM_SDCLK_1.

Is this case, how should I set DDR_SEL field and DSE field of IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P regisnter (chapter 36.4.353) in IMX6DQRM (rev.1)?

According to mode name, I think DDR_SEL= 11b from sel11, and DQE = 111b from (ds111).

Is this correct?

[Q2]

If the anwer for Q1 is correct, how about other setting?

Default values are set?

For example, there is no "odt" in the mode name, ODT = 000b in this case?

[Q3]

I use "ddr3_sel11_ds111_mio（DDR, 1.5V, ddr3 mode, 34 Ohm driver impedance)" for DRAM_SDQS0 write access, and "ddr3odt_t60_sel11_mi（DDR, 1.5V, ddr3 mode, 60 Ohm ODT)" for read access.

I think DQS is bi-drectional signal, also DQ, then can I set DRAM_SDQS0 IOMUX setting (e.g. DDR_SEL, DSE, etc) for write access and for read access individually?

[Q4]

I use "gpiohv_ds111_sr111_mio GPIO, 3.3V,extra drive,fast sr,max fsel" mode for ENET_TXD0.

When use this mode, how should I set each field of IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA00 register (chapter 36.4.317)?

Best Regards,

Satoshi Shimoda

[Yuri · Accepted solution]

Please use the Hardware Guide (Chapter 9 Understanding the IBIS Model) :

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

For example for GPIO signals :

dsxxx field relates to drive strength, controlled by the DSE bits (bits [5:3]) in the

IOMUXC_SW_PAD_CTL_PAD_<pad name>.

srxxx relates to

a) (first x in srxxx) slew rate Controlled by the SRE bit (bit 0) in the IOMUXC_SW_PAD_CTL_PAD_<padname>.

b) speed Controlled by the SPEED bits (bits [7:6]) in the IOMUXC_SW_PAD_CTL_PAD_<pad name>.

[satoshishimoda]

Hi Yuri,

Thank you for your reply.

[Q1] & [Q4] are now cleared by Hardware Development Guide.

Then, how about [Q2] & [Q3] ?

Best Regards,

Satoshi Shimoda

[satoshishimoda]

Hi Yuri,

Could you reply me about Q2 & Q3?

Best Regards,

Satoshi Shimoda

[Yuri]

2.
Other settings are described in the mentioned chapter. For example, section 9.5.1.1 "DDR [Model Selector]".

3.
Most "DRAM_SDQS0 IOMUX setting (e.g. DDR_SEL, DSE,)" relate to output parameters of the i.MX6.
(Input parameters, which are output for DDR devices,  should be set in DDRs)

[satoshishimoda]

Hi Yuri,

Thank you for your reply.

>2.

> Other settings are described in the mentioned chapter. For example, section 9.5.1.1 "DDR [Model Selector]".

Yes, almost setting is described in the chapter.

But I think there is no description about HYS bit setting.

And other model explanation does not mentioned a part of register setting also.

(e.g. section 9.5.2 [Model Selector] gpio does not mentions HYS, PUS, PUE, PKE, ODE settings).

So I want what settings are used for them.

Default values are used?

> 3

OK, I understand.

Best Regards,

Satoshi Shimoda

[Yuri]

HYS relates to input.

PKE = 0 (DISABLED — Pull/Keeper Disabled)

[satoshishimoda]

Dear Yuri,

Thank you for your reply.

Then, how about the bits for GPIO that are not described in IBIS model (HYS, PUS, PUE, PKE, ODE)?

According to your reply, HYS in DDR IOMUX register is used with default value, so the above bits for GPIO are also used with default value?

Best Regards,

Satoshi Shimoda

[Yuri]

Parameter HYS relates to input, IBIS model provides data (V-A curves) for output signals.

ODE (Open Drain Enable Field) = DISABLED. 

PKE = 0 (DISABLED — Pull/Keeper Disabled), this means PUS, PUE are not used.