I have an S12XE micro and I am trying to reverse engineer how the micro to DSP
SPI communication works.
Port M is configured to drive the SPI0 signals to a DSP (Balckfin) so it can
download the DSP image while the S12XE SPI0 is in Master mode.
So these are the PTM2/PTM3/PTM4/PTM5 pins (which are supposedly configured to drive
the SCK0/MISO0/SS0/MOSI0 signals to the DSP.
How is the "alternative" function of these pins programmed in the XE ?
How is the priority of the other "alternative" function of these pins determined?
If I enable just bit 6 (SPE) in the SPICR1 register, does that mean the SPI "alternative"
function is selected ?
Now if I enable the CAN2 module, does it mean the priority is now changed and the same
pins are driving TXCAN0/RXCAN0 ?
I am having trouble understandiung the concept of "routed" SPI 0, routed CAN0, etc. Below
is the excerpt from the S12XE documentation.
Port M general purpose input/output data—Data Register
Port M pin 5 is associated with the TXCAN signal of CAN2 and the routed CAN4 and CAN0, as well as with SCK
signals of SPI0. The CAN2 function takes precedence over the routed CAN0, routed CAN4, the routed SPI0 and the general purpose
I/O function if the CAN2 module is enabled. The routed CAN0 function takes precedence over the routed CAN4, the
routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. The routed CAN4 function
takes precedence over the routed SPI0 and general purpose I/O function if the routed CAN4 module is enabled. The
routed SPI0 function takes precedence of the general purpose I/O function if the routed SPI0 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.