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KL05 clocking difficulty

Question asked by Mark Butcher on Feb 20, 2014
Latest reply on Feb 27, 2014 by Mark Butcher

Hi All


The KL05 doesn't have a PLL and I am trying, for the first time, to work with the FLL, whereby I would like to use the external 32.768kHz crystal as oscillator to generate 48MHz.


At the moment I can't explain the followig behaviour:

1. - Out of reset the FLL output is being used, which is seen by the rate that the SYSTICK is firing (around 21.05MHz). This is expected.

2. - If I configure MCG_C2 ready for the 32kHz crystal and clear the IREFS bit in MCG_C1 the crystal circuit starts to oscillate. OSCINIT is seen being set in MCG_S and the IREFST is cleared (meaning that the oscillator is ready and the source of the FLL is now the "external reference clock"). This seems good.


But, since the external crystal is more accurate than the internal reference clock I would have expected the FLL output to now be more accurate (32.768kHz x 640 = 20.97MHz) but there was no change in it (but maybe difficult to measure).


As a test, I short circuited the 32kHz crystal so that it was no longer supplying a clock but the SYSTICK continued to operate and I could also look at the registers with the debugger. I could step code and the MCG status still showed the same state - suggesting FEE mode (FLL engaged external) "In FEE, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the external reference clock".


None of this is presently making sense. The MCG is confirming that it is using the external reference clock but this can't be the case because the processor still runs when this is physically removed. Since there was no operating frequency change it is quite certainly still using the FLL output, but derived from the internal 32kHz instead.

Furthermore, when attempting to move to any state not using the FLL output (CLKS not 0) the processor immediately "hangs"; debugger stops working.


Does anyone have an explanation as to what is actually going on??