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General switching specifications comprehension

Question asked by Christophe VIGNY on Feb 20, 2014
Latest reply on Feb 28, 2014 by Christophe VIGNY

I've got trouble understanding the General switching specification of the Kinetis devices.


For example the K20P144M120SF3, chap 5.3.2, Table 10 tells that "GPIO pin interrupt pulse width  Asynchrone (digital glitch and analog filter disabled) takes >16ns". I understand it's the minimum uptime of the PWM before the interrupt is raised.


But what I don't understand is the 8ns values for port rise and fall time. What do they represent?


What is tio50 and tio60 in that same table?