AnsweredAssumed Answered

Clock configuration problem with 100Mhz K20

Question asked by Tom Junkans on Feb 19, 2014
Latest reply on Feb 24, 2014 by Tom Junkans

I have a K20DX256VMD10 with a 30Mhz crystal and am trying to get it to run at 96Mhz core clock.

Using Processor Expert I selected PEE MCG mode and was able to set the core clock to 96Mhz.

I generated the code with PE and placed it in the appropriate place in my K20 project.

The PE code first attempts to set up FBE mode, and that is where it hangs up, waiting for the oscillator to run, and it never does.

The PE code:

/* Switch to FBE Mode */

   /* MCG_C2: RANGE=2,HGO=1,EREFS=1,LP=0,IRCS=1 */

   MCG_C2 = MCG_C2_RANGE(0x02) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK |  MCG_C2_IRCS_MASK;      

  /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=1,SC4P=1,SC8P=0,SC16P=1 */

   OSC_CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC16P_MASK;      

  /* SIM_SOPT2: MCGCLKSEL=0 */

   SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_MCGCLKSEL_MASK);                                  

  /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */

   MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK);                                  

  /* MCG_C4: DMX32=0,DRST_DRS=0 */

   MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));                                  

   /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV=9 */

   MCG_C5 = MCG_C5_PRDIV(0x09);                                  

  /* MCG_C6: LOLIE=0,PLLS=0,CME=0,VDIV=8 */

   MCG_C6 = MCG_C6_VDIV(0x08);                                  

  while((MCG_S & MCG_S_OSCINIT_MASK) == 0x00U) { /* Check that the oscillator is running */

   }

The red is where it hangs.

I have tried several PE clock settings and I can't get it to run past this when I select PEE for MCG mode. FEI MCG mode works fine but the core clock will only do 20+Mhz in that setting.

 

Any help is appreciated.

Thanks,

Tom

Outcomes