How is the ARM CP15SDISABLE connected on the Vybrid devices. This is referred to in the ARM cortex-A5 MPCore TRM version r0p1 in table 4-1 on page 4-3. It lists the following CP15 registers as locked by this signal.
- SCTLR System Control Register
- ACTLR Auxiliary Control Register
- TTBR0 Translation Table Base Register
- TTBCR Translation Table Base Control Register
- DACR Domain Access Control Register
- PRRR, NMRR Memory region remap
- VBAR Vector Base Address Register
- MVBAR Monitor Vector Base Address Register
The Vybrid bootloader/HAB could set this signal or perhaps it is available via some other module? Or it is hard coded in the Vybrid design?