I am checking some timing for constraints for my FPGA to MPC8313 interface. It looks to me like these two references disagree on the behavior of LWE and LOE with respect to LCLK.
REF 1 MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3 Figure 10-35 shows LWE falling on the rising edge of LCLK, the table 10-33 lists lots of tAWE options but the minimum is '1'.
REF 2 MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Table 45 / Figure 37 / Figure 38 shows the LOE LWE signals as launched from the MPC8313 on the falling edge of LCLK.
Perhaps my interpretation is wrong? Any help would be much appreciated.