I have a Vybrid VF6xx Board running Linux on the A5 and FreeRTOS on the M4. I implemented the Hardware Semaphores to synchronise the two Cores, but when i expect an Interrupt from A5 to M4 nothing happens on the M4 side. The "Sema4 unlocked" Interrupt doesn't show up as pending in the NVIC (Interrupt is enabled in the Interrupt Set-Enable Register). The Semaphores Processor n IRQ Notification Enable (SEMA4_CPnINE) and Semaphores Processor n IRQ Notification
(SEMA4_CPnNTF) Registers show the right values. On the other side, the Interrupt is coming through from the M4 to the A5. Additionally, if i set the Interrupt manually to pending in the NVIC, the Interrupt gets handled by my ISR on the M4.
What must i do to get the Interrupts working on the M4 side?
Are you routing the ISR to the M4? Make sure that the MSCM_IRSPRCn register is set correctly and that the NVIC enables the IRQ.
Remember that some IRQs can be shared and handled by both cores. But you have to configure this.
Best Regards,
Alejandro
Hi alejandrolozano,
i checked the MSCM_IRSPRCn register and it returns 0x0003 on address 0x40001888 (which is the SEMA4 Interrupt ID). The Interrupts still don't come through. Do you have any other Ideas?
I just checked the Reference Manual again and i need some clarification. Which "n" Number is the Sema4 Interrupt? Because according to the RM n could be 0-127 (see page 3503) or according to page 3508 0-111. Does the Interrupt even has such a Number? Because the RM also states that the Sema4 Interrupt is a Directed Interrupt, not a shared peripheral Interrupt which are stated as Inputs to Interrupt Router (see chapter 8.2.4 Interrupt Assignments).
Best Regards,
Simon
Hi,
You are correct in regards it is a direct interrupt. Therefore the interrupt router is not used. Sorry about that.
When you say that the SEMA4_CPnNTF registers show the correct value, what register are you specifically seeing?
Best Regards,
Alejandro
Hi,
the value ot the SEMA4_CP1NTF register is 0x8000 (i tried to lock Gate 3 which is locked by the Linux side. After the failed lock i unlock the gate on linux)
Best Regards,
Simon
I just wanted to make sure that the correct CPnNTF register was being debugged. But if you are trying to lock the gate3 should not be the 0x1000 the correct value? Also make sure that the correct NVIC->ISER register is set correctly.
Hi,
But if you are trying to lock the gate3 should not be the 0x1000 the correct value?
Yes, i also thougth that 0x1000 should be the correct value, but then i found this code in the Timesys BSP (core_mutex_sema4.c):
#if PSP_MQX_CPU_IS_VYBRID
static const int idx[16] = {3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12};
#else
static const int idx[16] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
#endif
....
// Enable 'unlocked' interrupt for this core
if (_psp_core_num()==0) {
component_ptr->DEVICE[core_num].SEMA4_PTR->CP0INE |= 1 << (SEMA4_NUM_GATES - 1 - idx[mutex_num]); //1 << (SEMA4_NUM_GATES-1-mutex_num);
} else {
component_ptr->DEVICE[core_num].SEMA4_PTR->CP1INE |= 1 << (SEMA4_NUM_GATES - 1 - idx[mutex_num]); //1 << (SEMA4_NUM_GATES-1-mutex_num);
}
i used the same in my code. So thats why the register value is 0x8000 for Gate 3. This Code Works, since the Interrupts coming through correctly from FreeRTOS to Linux.
I just describe you my debugging steps:
1. check if the NVIC_ISER0 value is correct:
0xE000E100: 0x0010
2. lock Gate 3 on linux side
SEMA4_Gate03 0x01
3. initialise the Sema4 on FreeRTOS side and check the SEMA4_CP1INE register:
x/1w 0x4001D048
0x4001D048: 0x80000000
4. try to lock the gate on FreeRTOS side
5. unlock the Gate on linux side and check the CP1NTF register value:
x/1w 0x4001D088
0x4001D088: 0x80000000
6. Check the pending Intterupt register of the NVIC:
x/1h 0xE000E200
0xE000E200: 0x0000
7. Check the Interrupt Active Bit Register, NVIC_IABR0:
x/1h 0xE000E300
0xE000E300: 0x0000
So the Interrupt is not pending, but the values of the SEMA4_CP1NTF and SEMA4_CP1INE registers are correct.
By the way i'm wondering why the RM states that the offset to the SEMA4_CP0INE Register is 40, but when i take a look at the SEMA4_MemMap struct in the "MVF50GS10MK50.h" the offset is 42?:
/** SEMA4 - Peripheral register structure */
typedef struct SEMA4_MemMap {
uint8_t GATE[16];
uint8_t RESERVED_0[50]; /* 48 */
uint16_t CP0INE; /**< Semaphores Processor n IRQ Notification Enable, offset: 0x40 */
uint8_t RESERVED_1[6];
uint16_t CP1INE; /**< Semaphores Processor n IRQ Notification Enable, offset: 0x48 */
uint8_t RESERVED_2[54];
uint16_t CP0NTF; /**< Semaphores Processor n IRQ Notification, offset: 0x80 */
uint8_t RESERVED_3[6];
uint16_t CP1NTF; /**< Semaphores Processor n IRQ Notification, offset: 0x88 */
uint8_t RESERVED_4[118];
uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */
uint8_t RESERVED_5[2];
uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
} volatile *SEMA4_MemMapPtr;
Best Regards
Simon