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Exploring Vybrid A5 QSPI XIP performance

Question asked by Nancy Jean Burkholder on Feb 5, 2014
Latest reply on Mar 5, 2014 by Anthony Huereca

I am exploring the Execution In Place (XIP) performance for an MQX application running on the Vybrid A5 core on a TWR-VF65GS10 board using the on-board QSPI memory. My test application utilizes the MQX shell, MFS, and SD card resources. I also have some custom code that allows me to access the MQX QSPI interface when the application runs out of SRAM. I discovered that MQX won't initialize the QSPI driver when executing out of QSPI; a restriction that makes sense but I wanted try it anyway.


Development in IAR 6.70 and using the quadspi_loader project in the Vybrid Sample Code to take the binary and flash it into the QuadSPI on the TWR-VF65GS10.


For my initial successful XIP build and boot I used quadspi_boot.c and a modified linker command file from the Vybrid Sample Code. The QSPI ran in SDR Single mode with the clock default in quadspi_boot.c set to 1. According to the Vybrid Reference Manual, page 902, this corresponds to an 18 MHz clock. I used a directory command to a subfolder on the SD card for a crude benchmark. Running from QSPI the "dir" command executed in about 2 seconds. In comparison, when running from SRAM the same command completed in about 85 ms.


In another thread,  Re: MQX application is not booting from QuadSPI_NAND flash, I found a boot configuration that ran in SDR Quad mode. I updated and reran my benchmark and the "dir" command executed in about 750 ms; a noticeable improvement. A setting in quadspi_conf indicated that a clock setting of 1 is 60 MHz.

  1,                      /* SCLK Freq - 60Mhz*/


Next I tried to improve the XIP performance. I increased SCLK frequency to 74 MHz and 99 MHz but neither configuration would boot. I also tried to set up quadspi to run in DDR mode without success by modifying the LUT to use DDR quad mode:


  0x04ED,       // CMD DDRQIOR

  0x2A18,       // ADDR_DDR (4) 24

  0x0C08,       // DUMMY 8

  0x3280,       // READ_DDR (4) 0x80

  0x2400,       // JMP_CS 0


I am still coming up to speed with QSPI so I wasn't surprised that my LUT sequence did not work.


I stepped through MQX startup and observed the I-cache being enabled. I plan to do some experiments to determine how using I-cache affects performance.



1. Can the SCLK frequency be increased? Is more needed than changing the quadspi_conf value? I stepped through MQX changing QSPI clock speed and the experience was character building.

2. Has anyone configured QSPI XIP with higher clock speed or DDR?

3. Are there any cache adjustments that would boost XIP performance?