I would like to configure the I2C0 port as slave and have it respond to two sequential addresses. The range address match capability appears able to do this. I would also like to differentiate between which register (A1 or RA) was matched. The I2Cx_S[RAM] bit appears to offer this capability. The reference manual states this bit is set if "Any nonzero calling address is received that matches the address in the RA register." However, an interrupt seems to get generated for the address in the A1 register, not the RA register. Can someone advise me on whether this I2Cx_S field can be used to differentiate between sequential slave addresses?