iMX6Q sabre lite board has no pcie ep device,Can iMX6Q pcie RC link up success?

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iMX6Q sabre lite board has no pcie ep device,Can iMX6Q pcie RC link up success?

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晨曹
Contributor I

Hello, every one.I'm a new developer.Now I use imx6Q sabre lite board.I want develop pcie RC mode on it.but now i have none pcie device connected.I download the newest

boundary-imx_3.0.35_4.1.0, but pcie rc cann't linkup successful.The error msg is:

PCIE: imx_pcie_pltfm_probe start link up.

link up failed, DB_R0:0x009e6c00, DB_R1:0x08200000!

IMX PCIe port: link down!

Can any one help me, Thanks!

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richard_zhu
NXP Employee
NXP Employee

No, you can't set up one pcie link only with PCIe RC represented.

Link is connected by RC and EP.

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Rita_Wang
NXP TechSupport
NXP TechSupport

Hi Chen,

Have you solved your problem? If you have would you please help click correct answer or help answer?

Thanks a lot~~

Best Regards

Dan

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晨曹
Contributor I

Hi Dan,We have already solved the problem .We buy a intel wireless net card connect to the board and then pcie link up successful.

 

cch7701 From: Dan WangDate: 2014-02-25 11:01To: 晨 曹Subject: Re: - iMX6Q sabre lite board has no pcie ep device,Can iMX6Q pcie RC link up success?

iMX6Q sabre lite board has no pcie ep device,Can iMX6Q pcie RC link up success?

reply from Dan Wang in i.MX Community - View the full discussion

Hi Chen,Have you solved your problem? If you have would you please help click correct answer or help answer?Thanks a lot~~Best RegardsDan

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Rita_Wang
NXP TechSupport
NXP TechSupport

Hi Chen,

I am glad to hear you have solved the problem. And thanks a lot for giving us response . Any other questions welcome to create new threads on i.mx community. We are on your side:smileyhappy:

Best Regards

Dan

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richard_zhu
NXP Employee
NXP Employee

No, you can't set up one pcie link only with PCIe RC represented.

Link is connected by RC and EP.

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Rita_Wang
NXP TechSupport
NXP TechSupport

Hi Hongxing,

Thanks a lot for your explanation and give the right direction.

Best Regards

Dan

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Rita_Wang
NXP TechSupport
NXP TechSupport

Hi 晨,

The PCIe clock output should be enabled in the code when the IMX6 worked as RC. Have you enabled the pcie clock yet?

Best Regards

Dan

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晨曹
Contributor I

Hi, DanAs you said, i found in 《i.MX 6Dual/6Quad Applications Processor Reference Manual》 pdf. Do you mean , i need to change CCM_CCGR register value?( In document these value default is all enable)

 

cch7701 From: Dan WangDate: 2014-02-17 14:21To: 晨 曹Subject: Re: - iMX6Q sabre lite board has no pcie ep device,Can iMX6Q pcie RC link up success?

iMX6Q sabre lite board has no pcie ep device,Can iMX6Q pcie RC link up success?

reply from Dan Wang in i.MX Community - View the full discussion

Hi 晨,The PCIe clock output should be enabled in the code when the IMX6 worked as RC. Have you enabled the pcie clock yet?Best RegardsDan

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Rita_Wang
NXP TechSupport
NXP TechSupport

Hi 晨,

You can do it in the function "static int _clk_pcie_enable(struct clk *clk)" in the file "clock.c" in source code(L3.0.35_4.1.0_130816_source I am using).

Set the "ANATOP_LVDS_CLK1_SRC_SATA" bit of the register "ANADIG_MISC1_REG" to enable the clock.

Best Regards

Dan

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晨曹
Contributor I

Hi Dan,this bit i have already set it.now i print it:iMX6 PCIe PCIe RC mode imx_pcie_pltfm_probe entering.enter clkpcie_enable function.CONFIG_IMX_PCIE_RC_MODE_IN_EP_RC_SYS = 1 .ANADIG_MISC1_REG = 0xf40c8160 . PLL8_ENET_BASE_ADDR = 0xf40c80e0 . ANADIG_MISC1_REG=0x80000000. write ANADIG_MISC1_REG = 0x8000040b . write PLL8_ENET_BASE_ADDR = 0x80182001 . PCIE: imx_pcie_pltfm_probe start link up.link up failed, DB_R0:0x00800300, DB_R1:0x08200000!IMX PCIe port: link down!IMX usb wakeup probe 

 

cch7701 From: Dan WangDate: 2014-02-18 15:21To: 晨 曹Subject: Re: - iMX6Q sabre lite board has no pcie ep device,Can iMX6Q pcie RC link up success?

iMX6Q sabre lite board has no pcie ep device,Can iMX6Q pcie RC link up success?

reply from Dan Wang in i.MX Community - View the full discussion

Hi 晨,You can do it in the function "static int clkpcie_enable(struct clk *clk)" in the file "clock.c" in source code(L3.0.35_4.1.0_130816_source I am using). Set the "ANATOP_LVDS_CLK1_SRC_SATA" bit of the register "ANADIG_MISC1_REG" to enable the clock.Best RegardsDan

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Rita_Wang
NXP TechSupport
NXP TechSupport

Hi 晨,

So sorry about my error answer, as Hongxing said you can't set up one pcie link only with PCIe RC represented. Link is connected by RC and EP. EP device is needed.

Best Regards

Dan

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