SDMA to connect ASRC pairs with I2S ports on i.MX6 Solo.

[robertobecchini]

Hello there,

I wanted to use SDMA to connect ASRC pairs (with multiple channels) with I2S ports on i.MX6 Solo.

One problem I have met is that the ASRC works like this (from RM) " When writing data to an input FIFO, you must ensure that it is in a predefined sequence. For example, when writing to an input FIFO, the sequence should be: channel_0, channel_1, channel_2,..., channel_n, channel_0, channel_1, channel_2, etc. Here channel_n stands for the data intended for the n-th channel. The hardware will re-allocate each data to its corresponding channel FIFO. ".

this means that I cannot use multichannel. I principle I would have to reorder all samplesfrom each ASRC channel  for SDMA one by one, makind SDMA usage  not efficient.

Does a design exist for my case where I can learn from? I suppose I should use the p_2_p RAM script.

Thanks for any help

Roberto

[leige-b42127]

we have no such use case in our code yet.

[YixingKong]

Robert

We have not got your response yet and will close the discussion in 3 days. If you still need help, please feel free to reply with an update to this discussion.

Thanks,

Yixing

[robertobecchini]

Hello Yixing,

I wanted to just post my apologizes here for being silent on the thread. I had a wrong setting in my profile so I did not receive any email notification about activities in this thread. And I was not polling Jive regularly.

Thanks for your patience with this.

I'll open another thread on ASRC since recently we have better defined our issue with p_2_p script and design.

Thanks again.

Roberto

[YixingKong]

Roberto

We are sorry for getting back to you so late. Are you still stuck with the issue? If you have somehow to resolved the

issue, can we close the discussion? If you still need help, please feel free to reply with an update to this discussion.

Thanks,
Yixing

[robertobecchini]

Hello Yixing,

the original issue was solved by redesigning our approach to audio. Yet that redesign was suboptimal even if ok for our purposes.

The summary of the problem is the following:

- each of the 10 channels per pair share one fifo per direction (I/O).

- each channel shall manage samples from/to fifo in rigid order.

- this order is driven by CPU (that is to be sure that each sample goes to the correct channel) or by SDMA (this is even more difficult to program since one does not want to really mess with the SDMA scripts). Also SDMA scripts execution is not preemptive; this exclude any sample management via scripts.

- In short, the use case for those 10 channels is weird and potentially involves CPU ovehead to feed channels in correct order.

- We hoped FSL have some design on how to actually use the channels in efficient and stright way.

- Our solution is to use une channel per pair per direction. The ASCc in this case can be used efficiently (one channel - one FIFO, FIFO wrote/read wia SDMA p_2_p script).

- Our conclusion (may be a wrong conclusion) is that having 10 channels per pair is near to useless. But again, we may have misunderstood the use cases for 10 channels per pair or mimssed some design consideration)

I hope you can still help here.

Bye

roberto

[YixingKong]

Robert

Had your issue got resolved? If yes, we are going to close the discussion in 3 days. If you still need help, please feel free to reply with an update to this discussion.

Thanks,

Yixing

[leige-b42127]

hi, it is not 10 channels per pair, we have 3 pairs,
A 3 channels

B 4 channels
C 3 channels

[YixingKong]

Roberto

I am going to branch your post into an internal group and have an engineer to reply/confirm on your design.

Thanks,
Yixing