I wanted to use SDMA to connect ASRC pairs (with multiple channels) with I2S ports on i.MX6 Solo.
One problem I have met is that the ASRC works like this (from RM) " When writing data to an input FIFO, you must ensure that it is in a predefined sequence. For example, when writing to an input FIFO, the sequence should be: channel_0, channel_1, channel_2,..., channel_n, channel_0, channel_1, channel_2, etc. Here channel_n stands for the data intended for the n-th channel. The hardware will re-allocate each data to its corresponding channel FIFO. ".
this means that I cannot use multichannel. I principle I would have to reorder all samplesfrom each ASRC channel for SDMA one by one, makind SDMA usage not efficient.
Does a design exist for my case where I can learn from? I suppose I should use the p_2_p RAM script.
Thanks for any help