I have a questions about i.MX6 IPU DI display clock polarity.
Please see chapter 38.5.193 in IMX6SDLRM Rev.1.
There is di0_polarity_disp_clk field, and description says as below.
DI0 Output Clock's polarity
This bits define the polarity of the DI0's clock.
1 The output clock is active high
0 The output clock is active low
But I did not understand what are "active high" & "active low".
What is changed by changing this polarity?
(e.g. active high = latch on rising edge, active low = latch on falling edge)