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Question, i.MX6DQ I2C clock setting

Question asked by AVNET JAPAN FAE (team share account) on Jan 28, 2014
Latest reply on Feb 9, 2014 by jimmychan

Hi Team,

 

I would like to ask about I2C clock setting.

My customer is trying to set I2C SCL clock frequency to 400KHz but cannot yet.

Now, the customer’s setting is as follows.

- CCM_CBCMR[PRE_PERIPH_CLK_SEL] = 00 (derive clock from PLL2 main 528MHz clock),

- CCM_CBCDR[AHB_PODF] = 011 (divide by 4),

- CCM_CBCDR[IPG_PODF] = 01 (divide by 2),

- CSCMR1[PERCLK_PODF] = 00000 (divide by 1)

Then PERCLK_CLK_ROOT is supposed to be 66MHz.

- IFDR=0x30 (66MHz / 400KHz = 160, IFDR=0x30)

As the result, I2C SCL clock was about 37KHz by the above settings.

Are there any misunderstandings on the above setting to set I2C SCL clock into 400KHz?

Please let me know the correct settings for 400KHz I2C SCL clock.

 

BR,

Miyamoto

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