I have the following questions:
in K20 Sub-Family Reference Manual, Rev. 2, Dec 2011
1.[5.4.1 Device clock summary Table 5-1. Clock Summary]
"MCGOUTCLK" is "Up to 120 MHz".
But, I want to output 144MHz from "MCGOUTCLK" using PLL0.
It is setable, is it out of a guarantee?
2.[25.5.3.1 "MCGOUTCLK Frequency = 128 MHz"]
Is it out of a guarantee?
I assume you speak of a 120MHz-rated K20 part. For the functions performed by MCGOUTCLK, said part-rating is certainly 'the legal limit'. The fact that an example in the RM (25.5.3.1) is 'not usable' by a particular chip is just a weakness of the manual-editors, much like the 100MHz 'Fsys' factor used throughout the SPI chapter, despite the fact that the 'fastest available' Kinetis bus clock is 75MHz. 'Actually usable' examples would certainly always be preferable...
In any case, there are some K60/61/70 parts rated at 150Mhz to net your 144MHz 'fully legal'.