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Question, i.MX6DQ DDR_SEL setting

Question asked by AVNET JAPAN FAE (team share account) on Jan 27, 2014
Latest reply on Jan 27, 2014 by Yuri Muhin

Hi All,

 

I would like to ask about IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII register of i.MX6DQ.

Should one set 11b into the DDR_SEL field in the case of using 1.8V/2.5V PHY?

Or, can DDR_SEL be default value(10b) regardless of the IO voltage of PHY?

Please give your answer to the above, and the explanation about this DDR_SEL setting as well.

 

BR,

Miyamoto

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