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MPC8641D Bus Error

Question asked by Jeff Baker on Jan 23, 2014
Latest reply on Jan 27, 2014 by lunminliang



We have a customer experiencing field issues on the MPC8641D that we believe may be a problem in the hardware.  The issue is critical for them but is extremely difficult to reproduce in a lab.  We have a test scenario that after many months has been reduced to an 8-hour failure.  Here is a brief description from our kernel engineer.  Worth noting is that when we disable speculative data prefetch (HID0[SPD]) on each core the issue can no longer be reproduced.


"With the S0 output, the MSSSR0 register is indicating the TEA signal was asserted but none of the registers that indicate things that feed into TEA are indicating an error. For the USB1 file, the EDR bit LAE bit is on but it’s occurring very early after a context synchronizing instruction (the SC instruction that started a kernel call sequence) and there’s no instructions anywhere in the vicinity that would cause a reference to the address that the ELADR register is showing."


"S0" and "USB1" being the names of the units involved in the test.