for our application , we need to enable ECC in OCRAM and DDR3 and we use Vybrid Tower kit TWR-VF65GS10.
1) On-Chip Memory Controllers
In chapter 65 of Vybrid reference manual version 5 , it is written
"... The OCRAM_sys ECC function can be summarized in the following steps. Consider reads and writes
For data writes received by the OCRAM_sys memory controller:
• If enabled, the ECC logic generates the 8-bit checkbit field based on the 29-bit address + 64-bit data
• The 64 data bits + 8 checkbits are stored in the memory ...
Note standard ECC operation requires that the entire memory be written during system startup to
“initialize” correct checkbit values for all locations before read operations can be checked. To assist in this
process, the device implements two independent control flags for each OCRAM_sys controller: one that
enables checkbit generation on writes and another to enable checking on read operations. The memory
initialization writes can be performed directly by a processor or an appropriately configured DMA
When I am reading the paragrah above , it seem we need to enable and modify some register to activate the ECC but I have searched in reference Manual and I didn't find how initialize the controller to activate ECC
What is the process to enable the ECC on OCRAM ?
I use the following procedure to enable ECC on DDR3
- I written the field ctrl-raw with value " ECC reporting is on, but no attempts to correct. or ECC reporting and correcting on" in register DDRMC_CR_57
- I set the field REDUC in register DDRMC_78
- I initialize the DDR3 with value 0xFFFFFFFF
- I enable the DDRMC interrupt to catch any issue
When I read the DDR3 memory with the following width32, 64, 128, 256 bits , it's OK
When I written the DDR3 memory with the following width 128, 256 bits , it's OK
but I written the DDR3 memory with the following width 32 or 64 bits , then the cortex A5 crashed and I need push the button reset
is that someone has already had this problem?
Thanks for any help