I am using the i.MX6S EIM to interface to an FPGA. I am using 16-bit synchronous reads on a multiplexed A/D bus mostly successfully. Occasionally when the processor core reads a 32-bit word from the FPGA instead of reading the word correctly it reads the first 16 bits twice in a row. I am using the WAIT signal to start the data transfer. I am not using continuous BCLK. The WAIT and DATA signals all transition very close to the falling edge of BCLK. I have tried varying the timing on the WAIT and DATA signals from the FPGA without making any difference. The problem only manifests itself when the processor core is busy with transmitting another file via Ethernet FTP at the same time it is reading data from the FPGA. The problem often disappears completely when I probe the BCLK line. Any suggestions?