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csb_clk maximum frequency of MPC8349E-667Mhz for DDR2 data rate of 400Mhz

Question asked by malli k on Jan 22, 2014
Latest reply on Jan 26, 2014 by malli k



This is my first post.

we are in the concept phase of our design.

we want to use MPC8349E-667Mhz and interface 8+1 , 8 bit DDR2 400Mhz chips to it.

When i see clocking options for the IC, i need one clarification.


We need to use 400Mhz data rate DDR2 SDRAM. So, 200Mhz is the DDR Clock frequency. from MPC8349EAEC Rev 13 datasheet, ddr_clk = csb_clk*(1+RCWL[DDRCM]), ddr_clk is the controller inside module clock, clock which driven onto the actual interface is ddr_clk/2, so, for our requirement ddr_clk = 400Mhz, and RCWL[DDRCM] can be either 0 or 1. From Table 57  csb_clk varies from 100-333 for 667 Mhz core clock part. So, csb_clk can't be 400Mhz( as it exceeds the spec).

So, csb_clk can be 200Mhz and RCWL[DDRCM]=1


But, MPC8349EA reference Manual Table 4-8 says "The 2:1 mode is useful mostly when for a 32-bit data bus memory device."


Is that mean whether i can't use RCWL[DDRCM]=1 for 64-bit interface of DDR2-SDRAM 400Mhz for MPC8349EC-667Mhz Part