AnsweredAssumed Answered

About the timing of the 24MHz Xtal stability and Reset de-assertion at a cold start of i.MX28

Question asked by yuuki on Jan 21, 2014
Latest reply on Feb 3, 2014 by yuuki

Would you teach about the timing of 24MHz Xtal oscillation stability and Reset de-assertion at a cold start of i.MX28?

 

The timing which I would like to know is the following.
Power-on(VDD5V power) => 24MHz Xtal oscillation stabile => Reset de-assertion

 

It is the purpose to check whether Xtal is oscillating correctly.


I am referring to the following.

IMX28CEC.pdf (Rev3):
- 3.1.7 Reset Timing(P.18)
"Because the i.MX28 is a PMU and an SoC, power-on reset is generated internally and there is no timing
requirement on external pins.
The i.MX28 can be reset by asserting the external pin RESETN for at least 100 mS and later deasserting
RESETN."

 

This time, VDD5V power pin is used.
In this case, according to 11.3.3 Power-Up Sequence of Reference manuals,  I think that the time to Reset de-assertion is the following.

VDD5V power pin > 4.25 V for 100 ms

 

However, I was not able to find the description about the relation between 24MHz Xtal statement and Reset de-assertion.

 

 

Best Regards,

Outcomes