- Board revision has been validated successfully.
- Boards will soon be available for purchasing.
- Presented files currently are in formal process of being published on official company web site.
(Materials attached have been implemented using Cadence tool, both latest Rev.16.6 and older Rev.16.2; use the latter to be converted into different formats or import into other schematic / layout tools.)
Main Vybrid-related revision modifications (with respect to Rev.G):
- DDR3: external termination deleted, Vref circuit simplified.
- Vybrid ballast transistor powered from 1.5V, not 3.3V.
- Optional "Virtual VF3xx" configuration created.
- Vybrid Power-On-Reset active timeout made longer to guarantee proper SD card initialization.
- Optional Ethernet MII interface added (DNP-ed 0-Ohm resistors).
- Filtering (series ferrite beads) added into x_AFE and x_ADC power rails for better performance.
- New button SW4 added to test low-power use cases.
Please, pay attention to new stackup and material of the board!
(Interestingly enough, one of the reasons for switching to new, high-frequency, board material was need to improve performance of the USB 2.0 interface...)
For reference only!
- Peak-to-peak ripple data for major power rails measured while running video clip included in supplied SD card (board as part of Tower - 2 Elevators + LCD modules powered from Vybrid module):
- VCC_1V2 (across C103) - 7.40mV,
- 1V5_DDR3 (across C51) - 16.83mV,
- VCC_1V5_SDRAM (across C10) - 18.60mV,
- VCC_3V3_ADC (across C171) - 4.97mV,
- VCC_3V3_AFE (across C56) - 10.6mV,
- VCC_3V3_MCU (across C43) - 10.6mV.
- Preliminary USB and radiation emission data with significant margins.
Original Attachment has been moved to: VYBRID_TWR_DESIGNFILES.zip