We have a custom IMX6Q board with 2GB of DDR3.
We boot from SD3 (4-bits) with BOOT_CFG[7:0] = 0100 0000; and BOOT_CFG2[7:0]= 0011 0000. BSP is based on Adeneo WEC7 BSP v1.7 (we have different IOMUX pinouts)- we haven’t made the 1GB-> 2GB ddr3 changes yet.
Problem: Our board doesn’t boot up consistently from SD3 (a micro-high capacity/4GB)- if we reset it (POR_B=0) repeatedly, it may or may not boot up. The likelihood of failure varies from board-to-board (some rarely fail and other do so ~50% of the time).
When it doesn’t boot, the SD3 clock is 50 MHz and there’s brief activity on the CMD/data lines before it stops.
In this state, we can still run the DDR stress test (USB serial) so the IMX6Q is still functional. (We’ve run the DDR stress test for hours w/o failing.)
When the board boots up , we can connect with JTAG (Lauterbach). But we can’t connect with JTAG when SD3 fails (USB serial download also won’t work).
When the board boots and JTAG connects, SRC_SBMR1= 0x 40 00 30 40.
ERR006282 seems N/A because the boot problem is too frequent. ERR004536 also seems N/A because we’re using SD (512 byte block size).
SD3 signal integrity is good and all SD3 traces are < 1 inch long.
POR_B looks fine (get same results with a rise-time < 5ns and with a very slow-rise time like Sabre).
IMX6Q version: MCIMX6Q5EYM10AC
PMIC version: PMPF0100F0AEP
PMIC voltages look good. Note: we’re using the new –A version (not fully tested since they were samples).
Anyone have any ideas?