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iMX6 DDR3 Routing on Sabre Dual Lite board

Question asked by Manie Coetzer on Jan 19, 2014
Latest reply on May 5, 2014 by Manie Coetzer

I have looked at the DDR3 routing on the Sabre Dual Lite reference design and the DDR3 routing rules in the Hardware Development Guide for i.MX6 Dual Lite.

First the length matching of the address and control signals for DDR3 is off by almost 700mil. Below is a table with the traces lengths measured on the reference board.

 

DRAM_A02366.603
DRAM_A12428.392
DRAM_A22485.718
DRAM_A32485.538
DRAM_A42740.291
DRAM_A52810.391
DRAM_A62815.121
DRAM_A72917.064
DRAM_A82809.252
DRAM_A92511.654
DRAM_A102256.097
DRAM_A112437.487
DRAM_A122481.741
DRAM_A132612.41
DRAM_A142546.543
DRAM_A152399.771
DRAM_CAS_B2235.064
DRAM_CS0_B2394.055
DRAM_RAS_B2286.018
DRAM_RESET_B2952.954
DRAM_SDBA02501.59
DRAM_SDBA12560.122
DRAM_SDBA22326.787
DRAM_SDCKE02235.184
DRAM_SDCLK02086.344
DRAM_SDCLK0_B2080.717
DRAM_SDCLK12113.077
DRAM_SDCLK1_B2113.37
DRAM_SDODT02717.477
DRAM_WE_B2341.702

 

Look at the different lengths between A7 which is the longest and CAS or CLK0.

 

Why is the length matching so far off compared to the required +/- 25mil as specified in the Hardware Development Guide.

 

The length matching of the individual data groups are within 10 mil  for each group.

 

Appreciate feedback on this because I am using the same concept as reference design but have some concerns about the length matching of address and control signals.

 

Thanks

Manie

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