I have looked at the DDR3 routing on the Sabre Dual Lite reference design and the DDR3 routing rules in the Hardware Development Guide for i.MX6 Dual Lite.
First the length matching of the address and control signals for DDR3 is off by almost 700mil. Below is a table with the traces lengths measured on the reference board.
Look at the different lengths between A7 which is the longest and CAS or CLK0.
Why is the length matching so far off compared to the required +/- 25mil as specified in the Hardware Development Guide.
The length matching of the individual data groups are within 10 mil for each group.
Appreciate feedback on this because I am using the same concept as reference design but have some concerns about the length matching of address and control signals.