Various QORIQ docs including the P2020 and P3041RMs state that "The DUART provides complete and sophisticated DMA support, which is described in FIFO Mode." and "The UFCR also selects the type of DMA signaling. The UDSR[RXRDY] indicates the status of the receiver FIFO. The DMA status registers (UDSR[TXRDY]) indicate when the transmitter FIFO is full. When in FIFO mode, data written to UTHR is placed into the transmitter FIFO. The first byte written to UTHR is the first byte onto the UART bus."
However, it isn't clear from the documentation of the DMA controller how to configure a channel so that it is throttled by the TXRDY and RXRDY signals for a specific UART.
Please can you clarify how this is done or point me to an App Note or S/W example.