QORIQ DUARTS with DMA

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QORIQ DUARTS with DMA

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JulianDay
Contributor I

Various QORIQ docs including the P2020 and P3041RMs state that "The DUART provides complete and sophisticated DMA support, which is described in FIFO Mode." and "The UFCR also selects the type of DMA signaling. The UDSR[RXRDY] indicates the status of the receiver FIFO. The DMA status registers (UDSR[TXRDY]) indicate when the transmitter FIFO is full. When in FIFO mode, data written to UTHR is placed into the transmitter FIFO. The first byte written to UTHR is the first byte onto the UART bus."

However, it isn't clear from the documentation of the DMA controller how to configure a channel so that it is throttled by the TXRDY and RXRDY signals for a specific UART.

Please can you clarify how this is done or point me to an App Note or S/W example.

Thanks,

Julian

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LPP
NXP Employee
NXP Employee

That's correct. I do not see reasons to handle QorIQ DUART traffic using DMA.

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720 Views
LPP
NXP Employee
NXP Employee

The comment from factory application team:

We are sorry for the confusion. The discussion of DUART DMA modes is specific to the DUART controller.The DUART controller programming model is designed to be compatible with the industry-standard National Semiconductor PC16550D DUART with 16 byte RX&TX FIFOs. That device has a DMA mode which causes it to signal (via dedicated RXRDY# and TXRDY# signals) an external DMA module to empty the RX FIFO or fill the TX FIFO when a programmed threshold has been reached. The text in the DUART chapter has been written to be consistant with that programming model.

In the case of the DUART controller on P2020, the dedicated RXRDY#/TXRDY% signalling is replaced with status bits in the DMA Status Registers (UDSRn) that can be used to generate an interrupt to the programmable interrupt controller (PIC) which can then interrupt the processor core. The processor core as part of the interrupt service routine can then access the DUART FIFOs via the URBRn/UTHRn registers or it can program one of the DMA channels to handle the access to those registers.

So, in the P2020 SoC context, there is no direct link between the FIFO status (RXRDY/TXRDY) and a dedicated DMA controller resource on the chip. 

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JulianDay
Contributor I

Thanks.

So, my understanding is that first statement which I quoted (from right at the end of the DMA controller chapter) is actually incorrect, since there is no functionality to link the DMA controller and the DUART.

Do you think that there is any gain to be made from using the DMA controller without this kind of hardware signalling? Given that you need to read the IIRs for each controller and handle that anyway, since these 'DMA' signals aren't a separate interrupt. Reading the UDSRs and doing appropriate DMA programming is all extra work; it might be more efficient just to use the CPU to fill or drain the FIFOs.

Thanks again,

Julian

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721 Views
LPP
NXP Employee
NXP Employee

That's correct. I do not see reasons to handle QorIQ DUART traffic using DMA.

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