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SRTC of i.MX51 is not Enabled at cold start

Question asked by yuuki on Jan 15, 2014
Latest reply on Feb 11, 2014 by yuuki
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I have a problem that SRTC is not Enabled at cold start.

 

I checked the status register. It seems that SRTC has shifted to the Failure state, because it detected some alarms.

LPSR (Status Reg) = 0x00000065

- EAD bit = 1: Security alarm detected

- TR bit = 1: Counter has reached its maximum value

- CTD bit = 1: Clock Tampering Detected.

- TRI bit = 1: Time read is invalidated.

 

LPGR (General Purpose Reg) = 0x82400000

- SW_ISO = 1: SRTC is isolated from the rest of the SoC.

 

Is it able to be enabled when SRTC is in a Failure state?

 

Best Regards,

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