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DDRMC_PHY02 Register Reserved Bits?

Question asked by rmcginnis on Jan 15, 2014
Latest reply on Jan 16, 2014 by Naoum Gitnik

The file ddr.c included with the Freescale tower example source code sets 0x01210080 in the PHY02,18,&34 registers.  When looking at the Vybrid reference manual (Rev 5, 07/2013) bits 7, 16 and 24 are set within the Reserved areas of the PHY Register 2 is set.  When I write 0xFFFFFFFF to that register I'm able to read back 0xFFFFFFFF which doesn't agree with the reference manual documentation.

 

What are the reserved register bits that are set within the PHY02 register?  Is the reference manual documentation correct?

 

 

ddr.c - source code

      #define PHY_CTRL   0x01210080

 

  // phy_gate_lpbk_ctrl_reg freq set 0

    reg32_write(DDR_PHY002, PHY_CTRL);    // read delay bit21:19

    reg32_write(DDR_PHY018, PHY_CTRL);    // phase_detect_sel bit18:16

    reg32_write(DDR_PHY034, PHY_CTRL);    // bit lpbk_ctrl bit12




phy02.png

 

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