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MC9S12NE64 - MII MRADR Register Description

Question asked by Kevin Huffman on Jan 9, 2014
Latest reply on Jan 14, 2014 by iggi


I am looking for additional documentation / app notes on the MC9S12NE64 MII Managment Register descriptions.  Specifically, the MRADR (MII Management Register Address) bit fields RADDR.  When a value is written to the RADDR field, what registers are actually accessed?  Based on sample code provided with the MC9S12NE64, it appears the MRADR and MPADR are used in conjunction to access PHY registers (but per my prior statement I'm unable to find a list / description of the PHY registers accessed through the MRADR register).  In the example code, a higher level function call that writes data to the MII includes (within the write function) a MII read with RADDR set to 0x10.  The sample header file documents this location as the PHY interrupt register.  It really doesn't make sense to me why a read of the interrrupt register would be needed after the write (the code is not interrupt driven).

The code snippet is:

 

unsigned char MIIwrite(unsigned char mpadr, unsigned char mradr, unsigned int mwdata)

{

unsigned int temprdata;

 

MPADR = mpadr;          //select physical address, 0 = internal PHY

MRADR = mradr;         //selects register on PHY, but no information on these registers can be found

MWDATA = mwdata;     //place 16 bit data into MII buffer

MCMST = MCMST|0x01;     //execute write operation

while(!(IEVENT&0x80);             //wait for write to complete

IEVENT = IEVENT&~0x80;              //clear write complete flag

while(!(MIIread(PHY_ADDRESS, PHY_REG_IR, &temprdata));    //PHY_ADDRESS = 0 for internal PHY, PHY_REG_IR is the phy interrupt register according to sample code documentation??  Don't understand why the read of the

                                                                                              //interrupt  reg & can't find any documentation on the interrupt reg or other PHY regs

}

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