I'm trying to program a custom board based on the KL46. However the reset signal for the SWD port is stuck at logic LOW. My programmer is a P&E Multilink FX. I can successfully program my test app on an FRDM-KL46Z. But I get the following error on CW 10.5's console when I try to program my custom KL46 board:
"can not enter background mode"
Then CW 10.5 displays the "P&E Connection Assistant" dialog offering me to "Retry", "Abort" and/or edit the connection settings. If I click "Abort" I get a "Problem Occured" dialog with the following explanation:
"Error launching imatec-firmware_FLASH_PnE U-MultiLink
ARM GDI Protocol Adapter : Can't connect. The Debugger can not connect to the P&E device"
I found a PDF guide by P&E Micro with troubleshooting steps to follow when the background mode cannot be entered:
1) Check for power on. Checked! Power is on.
2) Make sure the processor oscillator is running. Checked! The external oscillator is not running but I believe this is normal since it should be the KL46's responsibility to cause the external crystal oscillator to run. I'm using an 8 MHz crystal.
3) Look up the startup sequence for your microprocessor:
3.a) Reset is driven low (to processor). Checked! **It always stays at low.**
3.b) Activity appears on TCK, TDI and TDO. Cheked! I'm using the SWD interface and I see that SWD_CLK and SWD_DIO give a burst sequence and then the lines go back to logic low and stay like that.
3.c) Reset is released by the interface and will go high. Checked! **Reset always stays low.**
3.d) Activity appears on TCK, TDI and TDO (Debug activity). Checked! The SWD_CLK and SWD_DIO lines stay low indefinitely.
In contrast, the FRDM-KL46Z successfully passes these checks and I have been able to take oscilloscope captures of both the successful FRDM-KL46Z SWD programming attempts and the unsuccessful custom KL46 board SWD programming attempts. The burst sequence produced by the P&E Multilink FX on the SWD lines looks the same for both boards with the following exceptions:
The reset line is never asserted in the custom board and the SWD clock and data lines stay indefinitely low after the initial burst sequence.
In contrast, the burst sequence with the FRDM-KL46Z shows that the reset line is asserted at the beginning of the sequence and then it is released to logic HIGH at the end of the sequence. This is followed by an idle period and then new burst sequences are exchanged between the FRDM-KL46Z and the P&E Multilink FX.
I already checked that the SWD pins from the Multilink unit have continuity all the way the correct KL46 pins. I'm using a 64-pin LQFP package.
The pins are connected as follows:
TVCC to OUT3V3
GND to my custom board's GND plane (For example, I checked that the GND has continuity with the VSS pins on the KL46)
SWD_CLK/TCK to PTA0
SWD_DIO/TMS to PTA3
RESET_n to PTA20
TDI to PTA1
TDO to PTA2
The TDI and TDO lines are connected because that's what's shown in the FRDM-KL46Z's reference schematic. I checked these lines on an oscilloscope and I can tell that neither the FRDM-KL46Z or the custom board show any activity on them.
Thanks in advance, any suggestions are welcome! I will let you know if I find the solution.