Editing the LCF in CW

[tektronix]

I am using TRK-USB-MPC5643L. Here is the linker command file for my project. Below I have pasted the linker command file. I am using the processor in Dual core mode. The core 0 is running from 0x40000000 where as some variables for core 1 are also running from 0x40000000 memory region. Now I want to edit it such a way that all the code of core 0 runs from its memory region of 0x400000000 and core 1 runs from its memory region of 0x50000000. I don't want any variable or function to be defined in the area of the other core. Can anyone help me with this>

/* lcf file for MPC5643L processors, running in DPM (dual core) mode        */

/*                                                                          */

/* Note internal memory configurations vary among the various family        */

/* devices.                                                                 */

/*                                                                          */

/*   +-----------+------------+                                */

/*   |  Device   | MPC5643L   |                                 */

/*   +-----------+------------+                                 */

/*   |SRAM/Flash | 128KB/1MB  |                                 */

/*   |           |            |                               */

/*   +-----------+------------+                               */

/*                                                                          */

/* These memory definitions will allow the stationery example to run on     */

/* the smallest, i.e. MPC5643L device's internal memory (1MB   Flash,       */

/* 128KB SRAM).                                                              */

MEMORY

{

    pseudo_rom:             org = 0x40000000,   len = 0x00006800

    init:                   org = 0x40006800,   len = 0x00000800

    exception_handlers_p0:  org = 0x40007000,   len = 0x00001000

    internal_ram:          org = 0x40008000,   len = 0x00005000

    heap  :                 org = 0x4000D000,   len = 0x00001000 /* Heap start location */

    stack :                 org = 0x4000E000,   len = 0x00002000 /* Start location for Stack */

    /* Split map for the second core */

    exception_handlers_p1:  org = 0x50000000,   len = 0x00001000

    internal_ram_p1:      org = 0x50001000,   len = 0x0000B000

    heap_p1  :              org = 0x5000C000,   len = 0x00001000

    stack_p1 :              org = 0x5000D000,   len = 0x00003000

}

SECTIONS

{

    GROUP : {

      .init  : {}

      .init_vle (VLECODE) : {

        *(.init)

        *(.init_vle)

      }

    } > init

    GROUP : {

      .ivor_branch_table_p0 (VLECODE) ALIGN (2048) : {}

      .intc_hw_branch_table_p0 ALIGN (2048) : {}         

      .__exception_handlers_p0 (VLECODE) : {}

    } > exception_handlers_p0

    GROUP : {

      .ivor_branch_table_p1 (VLECODE) ALIGN (2048)  : {}

      .intc_hw_branch_table_p1 ALIGN (2048) : {} 

      .__exception_handlers_p1 (VLECODE) : {}

    } > exception_handlers_p1

    GROUP : {

      .intc_sw_isr_vector_table_p0 ALIGN (2048) : {}

      .intc_sw_isr_vector_table_p1 ALIGN (2048) : {}

        .text (TEXT) ALIGN(0x1000) : {}

        .text_vle (VLECODE) ALIGN(0x1000): {

             *(.text)

             *(.text_vle)

         }

        .rodata (CONST) : {

            *(.rdata)

            *(.rodata)

        }

        .ctors : {}

        .dtors : {}

        extab : {}

        extabindex : {}

    } > pseudo_rom

    GROUP : {  

       .__uninitialized_intc_handlertable ALIGN(0x10) : {}

       .data   : {}

       .sdata  : {}

       .sbss   : {}

       .sdata2 : {}

       .sbss2  : {}

       .bss    : {}

    } > internal_ram

}

/* Freescale CodeWarrior compiler address designations */

_stack_addr = ADDR(stack)+SIZEOF(stack);

_stack_end  = ADDR(stack);

_heap_addr  = ADDR(heap);

_heap_end   = ADDR(heap)+SIZEOF(heap);

_stack_addr_p1 = ADDR(stack_p1)+SIZEOF(stack_p1);

_stack_end_p1  = ADDR(stack_p1);

_heap_addr_p1  = ADDR(heap_p1);

_heap_end_p1   = ADDR(heap_p1)+SIZEOF(heap_p1);

/* Exceptions Handlers Location (used in Exceptions.c for IVPR initialization) */

EXCEPTION_HANDLERS = ADDR(exception_handlers_p0);

EXCEPTION_HANDLERS_P1 = ADDR(exception_handlers_p1);

[ZhangJennie]

I suggest you refer this document

[stanish]

Hi,

If you intend to run two completely separate tasks (each executed on separate core) you can split your application into 2 separate projects. e.g.:

lcf file of project for core 0:

MEMORY

{

    pseudo_rom:            org = 0x40000000,  len = 0x00006800

    init:                  org = 0x40006800,  len = 0x00000800

    exception_handlers_p0: org = 0x40007000,  len = 0x00001000

    internal_ram:          org = 0x40008000,  len = 0x00005000

    heap  :                org = 0x4000D000,  len = 0x00001000 /* Heap start location */

    stack :                org = 0x4000E000,  len = 0x00002000 /* Start location for Stack */

}

SECTIONS

{

    GROUP : {

      .init  : {}

      .init_vle (VLECODE) : {

        *(.init)

        *(.init_vle)

      }

    } > init

    GROUP : {

      .ivor_branch_table_p0 (VLECODE) ALIGN (2048) : {}

      .intc_hw_branch_table_p0 ALIGN (2048) : {}      

      .__exception_handlers_p0 (VLECODE) : {}

    } > exception_handlers_p0

    GROUP : {

      .intc_sw_isr_vector_table_p0 ALIGN (2048) : {}

      .text (TEXT) ALIGN(0x1000) : {}

      .text_vle (VLECODE) ALIGN(0x1000): {

            *(.text)

            *(.text_vle)

        }

        .rodata (CONST) : {

            *(.rdata)

            *(.rodata)

        }

        .ctors : {}

        .dtors : {}

        extab : {}

        extabindex : {}

    } > pseudo_rom

GROUP : { 

       .__uninitialized_intc_handlertable ALIGN(0x10) : {}

       .data   : {}

       .sdata  : {}

       .sbss   : {}

       .sdata2 : {}

       .sbss2  : {}

       .bss    : {}

    } > internal_ram

}

and second project for core 1 should be placed into core 1 memory block:

MEMORY

{

    pseudo_rom:            org = 0x50000000,  len = 0x00006800

    init:                  org = 0x50006800,  len = 0x00000800

        exception_handlers_p1: org = 0x50007000,  len = 0x00001000

    internal_ram:          org = 0x50008000,  len = 0x00005000

    heap:                  org = 0x5000D000,  len = 0x00001000

    stack:                 org = 0x5000E000,  len = 0x00002000

}

...

So there are two .elf files that do not overlap in RAM memory which you can debug.

Hope it helps...

Stan