We are having an issue with burst transfers on the Flexbus. We would like to transfer four 32 bit double words per burst. This is necessary to obtain the data throughput we need in our system. The reference manual does not show any specific timing diagrams for this type of transfer, but it does state in a table in section 184.108.40.206 that a port size of 32 bits can burst with 4 beats. Discussions with local FAEs suggest that this should work as we understand it.
I’ve defined chip select 2 for write burst accesses in our system. To that end, the chip select has been programmed as follows:
Register Value Description
FB_CSAR2 0x30020000 Sets the base address of the chip select to 0x30020000.
FB_CSCR2 0x00000108 No wait states, Burst writes enabled, auto terminated accesses
FB_CSMR2 0x00000001 Enables the chip select for range 0x30020000 to 0x3002FFFF, write are allowed.
Additionally, we’ve set up a DMA to move multiple 32 bit double words out the port. When the DMA destination data transfer size is 32-bit, only single Flexbus accesses are observed. Does the DMA destination data transfer size need to be 32-byte to support bursting on the Flexbus? When we set the DMA destination data transfer size to 32-byte the DMA stalls and no transfers on the bus are observed. How does the DMA need to be configured to allow the Flexbus to transfer four 32-bit double words per burst?